1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, for example, to a nonvolatile semiconductor memory such as a NAND flash EEPROM of a charge trap type or a floating gate type.
2. Background Art
In general, when forming bit line contact plugs in a NAND device, contact holes are formed on respective active regions between select gates, a barrier metal is deposited on bottom and side surfaces of the contact holes, and a plug material is buried in the contact holes via the barrier metal. In such a manner, the contact plugs each including a barrier metal layer and a plug material layer is formed in the contact holes (see, JP-A 2009-10011 (KOKAI), for example).
However, if such a structure is adopted in a fine NAND device, the percentage of the barrier metal layer that occupies a horizontal cross section of a contact plug (i.e., a cross section perpendicular to a current flowing direction) becomes large. This is because the width of the active region and the diameter of the contact plug become smaller by shrinking in a size of the NAND device. The larger percentage of the barrier metal layer that occupies the cross section of the contact plug results in a problem of an increase in resistivity of the contact plug, for example.